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| DS1004 5-Tap High Speed Silicon Delay Line www.dalsemi.com FEATURES All-silicon timing circuit Five equally delayed clock phases per input Precise tap-to-tap delay tolerances of 0.5, 0.75, or 1 ns Input-to-tap 1 delay of 5 ns Delay tolerances of 1.5 ns over temperature and voltage Leading and trailing edge precision preserves the input symmetry CMOS design with TTL compatibility Standard 8-pin DIP and 150 mil 8-pin SOIC Vapor phase, IR and wave solderable Available in Tape and Reel PIN ASSIGNMENT IN TAP 2 TAP 4 GND 1 2 3 4 8 7 6 5 VCC TAP 1 TAP 3 TAP 5 DS1004M 8-Pin DIP (300-mil) See Mech. Drawings Section IN TAP 2 TAP 4 GND 1 2 3 4 8 7 6 5 VCC TAP 1 TAP 3 TAP 5 DS1004Z 8-Pin SOIC (150-mil) See Mech. Drawings Section PIN DESCRIPTION TAP 1-5 VCC GND IN - TAP Output Number - +5 Volt Supply - Ground - Input DESCRIPTION The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4, or 5 ns tap-to-tap delays within a standard part family. The device is Dallas Semiconductor's fastest 5-tap delay line. It is available in a standard 8-pin DIP and 150 mil 8-pin mini-SOIC. The device features precise leading and trailing edge accuracies and has the inherent reliability of an all-silicon delay line solution. The DS1004 is specified for tap-to-tap tolerances as shown in Table 1. Each device has a minimum inputto-tap 1 delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4, or 5 ns. See Table 1 for details. Tolerance over temperature and voltage is 1.5 ns. Nominal tap-to-tap tolerances range from 0.5 ns to 1.0 ns. Each output is capable of driving up to 10 LS loads. For customers needing non-standard delay values, the Late Package Program (LPP) is available. Customers may contact Dallas Semiconductor at (972) 371-4348 for further details. 1 of 6 111799 DS1004 PART NUMBER TOLERANCE TABLE Table 1 INPUT-TO-TAP PART NUMBER TOLERANCE NOMINAL VARIATION OVER TEMP & VOLTAGE INCREMENT TAP-TO-TAP TOLERANCE NOMINAL VARIATION OVER TEMP & VOLTAGE DS1004M-2 DS1004M-3 DS1004M-4 DS1004M-5 DS1004Z-2 DS1004Z-3 DS1004Z-4 DS1004Z-5 5 1.5 ns 5 1.5 ns 5 1.5 ns 5 1.5 ns 5 1.5 ns 5 1.5 ns 5 1.5 ns 5 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 2 ns 3 ns 4 ns 5 ns 2 ns 3 ns 4 ns 5 ns 0.5 ns 0.75 ns 1.0 ns 1.0 ns 0.5 ns 0.75 ns 1.0 ns 1.0 ns 0.75 ns 0.75 ns 0.75 ns 0.75 ns 0.75 ns 0.75 ns 0.75 ns 0.75 ns NOTES: 1. Nominal conditions are +25C and VCC = +5.0 volts. 2. Temperature and voltage variations cover the range from VCC=5.0 volts =5% and temperature range from 0C to +70C. 3. Delay accuracy for both leading and trailing edges. PART NUMBER DELAY TABLE Table 2 PART NUMBER NOMINAL VALUES (FOR REFERENCE ONLY) INPUT-TO-TAP1 INPUT-TO-TAP2 INPUT-TO-TAP3 INPUT-TO-TAP4 INPUT-TO-TAP5 DS1004M-2 DS1004M-3 DS1004M-4 DS1004M-5 DS1004Z-2 DS1004Z-3 DS1004Z-4 DS1004Z-5 5 ns 5 ns 5 ns 5 ns 5 ns 5 ns 5 ns 5 ns 7 ns 8 ns 9 ns 10 ns 7 ns 8 ns 9 ns 10 ns 9 ns 11 ns 13 ns 15 ns 9 ns 11 ns 13 ns 15 ns 11 ns 14 ns 17 ns 20 ns 11 ns 14 ns 17 ns 20 ns 13 ns 17 ns 21 ns 25 ns 13 ns 17 ns 21 ns 25 ns LOGIC DIAGRAM 2 of 6 DS1004 DS1004 TEST CIRCUIT Figure 1 TEST SETUP DESCRIPTION Figure 1 illustrates the hardware configuration used for measuring the timing parameters of the DS1004. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected to the output. The DS1004 output taps are selected and connected to the interval counter by a VHF switch control unit. All measurements are fully automated with each instrument controlled by the computer over an IEEE 488 bus. 3 of 6 DS1004 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current -1.0V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds 50 mA for 1 second * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage Active Current High Level Input Voltage Low Level Input Voltage Input Leakage High Level Output Current Low Level Output Current SYM VCC ICC VIH VIL II IOH IOL 0.0V VI VCC VCC=4.75V VOH=4V VCC=4.75V VOL=0.5V TEST CONDITION VCC=5.25V Period=1 s 2.2 -0.5 -1.0 MIN 4.75 (0C to 70C; VCC = 5.0V 5%) TYP 5.00 35 MAX 5.25 75 VCC + 0.5 0.8 1.0 -1.0 UNITS V mA V V A mA mA NOTES 1 1 1 12 AC ELECTRICAL CHARACTERISTICS PARAMETER Period Input Pulse Width Input to Tap 1 Output Delay Tap-to-Tap Delays Output Rise or Fall Time Power-up Time SYMBOL tPERIOD tWI tPLH, tPHL tPLH tOR, tOF tPU MIN 4 (tWI) 40% of Tap 5 tPLH (TA = 25C; VCC = 5V 5%) TYP MAX UNITS ns ns ns ns ns ms NOTES 3 3 2 2 Table 1 Table 1 2.0 2.5 100 CAPACITANCE PARAMETER Input Capacitance SYMBOL CIN MIN TYP MAX 10 (TA = 25C) UNITS pF NOTES 4 of 6 DS1004 NOTES: 1. All voltages are referenced to ground. 2. VCC=5 volts and 25C. Delay accuracy on both the rising and falling edges within tolerances given in Table 1. 3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application sensitive with respect to decoupling, layout, etc. TEST CONDITIONS INPUT: Ambient Temperature: Supply Voltage (VCC): Input Pulse: 25C =3C 5.0V =0.1V High = 3.0V =0.1V Low = 0.0V =0.1V 50 ohm max. 3.0 ns max. (measured between 0.6V and 2.4V) 500 ns 1 s 15 pF Source Impedance: Rise and Fall Time: Pulse Width: Pulse Period: Output Load Capacitance: OUTPUT: Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on the rising and falling edge. NOTE: Above conditions are for test only and do not restrict the devices under other data sheet conditions. TIMING DIAGRAM: DS1004 INPUT TO OUTPUTS 5 of 6 DS1004 TERMINOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of the output pulse. tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the falling edge of the input pulse and the 1.5V point on the falling edge of the output pulse. 6 of 6 |
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